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1 THERMAL CONTROL SYSTEMS, MODELS, AND MANUFACTURING PROCESSES IN LITHOGRAPHY TECHNICAL FIELD 5 [0001] The description herein relates generally to lithography in semiconductor manufacturing, and more particularly, to computational lithography. BACKGROUND [0002] A lithographic projection apparatus can be used, for example, in the manufacture of integrated 10 circuits (ICs). A patterning device (e.g., a mask) may include or provide a pattern corresponding to an individual layer of the IC (“design layout”), and this pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the pattern on the patterning device. In general, a single substrate contains a plurality of adjacent target 15 portions to which the pattern is transferred successively by the lithographic projection apparatus, one target portion at a time. In one type of lithographic projection apparatus, the pattern on the entire patterning device is transferred onto one target portion in one operation. Such an apparatus is commonly referred to as a stepper. In an alternative apparatus, commonly referred to as a step-and- scan apparatus, a projection beam scans over the patterning device in a given reference direction (the 20 “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction. Different portions of the pattern on the patterning device are transferred to one target portion progressively. Since, in general, the lithographic projection apparatus will have a reduction ratio M (e.g., 4), the speed F at which the substrate is moved will be 1/M times that at which the projection beam scans the patterning device. More information with regard to lithographic 25 devices can be found in, for example, US 6,046,792, incorporated herein by reference in its entirety. [0003] Prior to transferring the pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures (“post-exposure procedures”), such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the transferred pattern. This 30 array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the 35 substrate. These devices are then separated from one another by a technique such as dicing or sawing, such that the individual devices can be mounted on a carrier, connected to pins, etc. 2 [0004] Manufacturing devices, such as semiconductor devices, typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the devices. Such layers and features are typically manufactured and processed using, e.g., deposition, lithography, etch, chemical-mechanical polishing, and ion 5 implantation. Multiple devices may be fabricated on a plurality of dies on a substrate and then separated into individual devices. This device manufacturing process may be considered a patterning process. A patterning process involves a patterning step, such as optical and/or nanoimprint lithography using a patterning device in a lithographic apparatus, to transfer a pattern on the patterning device to a substrate and typically, but optionally, involves one or more related pattern 10 processing steps, such as resist development by a development apparatus, baking of the substrate using a bake tool, etching using the pattern using an etch apparatus, etc. [0005] Lithography is a central step in the manufacturing of device such as ICs, where patterns formed on substrates define functional elements of the devices, such as microprocessors, memory chips, etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro- 15 electro mechanical systems (MEMS) and other devices. [0006] As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced. At the same time, the number of functional elements, such as transistors, per device has been steadily increasing, following a trend commonly referred to as “Moore’s law.” At the current state of technology, layers of devices are manufactured using 20 lithographic projection apparatuses that project a design layout onto a substrate using illumination from a deep-ultraviolet illumination source, creating individual functional elements having dimensions well below 100 nm, i.e. less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source). [0007] This process in which features with dimensions smaller than the classical resolution limit of a 25 lithographic projection apparatus are printed, is commonly known as low-k1 lithography, according to the resolution formula CD = k1×λ/NA, where λ is the wavelength of radiation employed (currently in most cases 248nm or 193nm), NA is the numerical aperture of projection optics in the lithographic projection apparatus, CD is the “critical dimension”–generally the smallest feature size printed–and k1 is an empirical resolution factor. In general, the smaller k1 the more difficult it becomes to 30 reproduce a pattern on the substrate that resembles the shape and dimensions planned by a designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the lithographic projection apparatus, the design layout, or the patterning device. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting patterning devices, 35 optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, or other methods generally defined as “resolution enhancement techniques” (RET). 3 [0008] OPC and other RET utilize robust electronic models that describe the lithography process. Calibration procedures for such lithography models are thus desired that provide valid, robust and accurate models across the process window. Currently, calibration is done using a certain number of 1-dimensional and/or 2-dimensional gauge patterns with wafer measurements. More specifically, the 5 1-dimensional gauge patterns include line-space patterns with a varying pitch and critical dimension (CD), isolated lines, multiple lines, etc. The 2-dimensional gauge patterns typically include line-ends, contacts, and randomly selected SRAM (Static Random Access Memory) patterns. SUMMARY 10 [0009] It is desirable to reduce or otherwise control aberration drift so as to reduce defects when manufacturing devices, such as semiconductor devices, using the lithography process. One cause of aberrations drift, is undesired or unexpected thermal changes to one or more components of the optical projection system. For example, as light (e.g., EUV light, DUV light) is incident on various optical elements of the optical projection system, those optical elements may “heat” up. The 15 “heating” of the optical elements may cause the optical elements to deform, which results in changes to a wavefront provided by the optical projection system for patterning devices. [0010] According to some embodiments, there is a method for determining one or more process parameters. The method includes obtaining a wavefront drift of a wavefront provided by an optical projection system of a semiconductor processing apparatus. The wavefront drift may be determined 20 based on a comparison of wavefront data representing the wavefront and target wavefront data. The method may further include determining the one or more process parameters based on the wavefront drift. The one or more process parameters may include parameters associated with a thermal device, where the thermal device may be configured to provide thermal energy (e.g., provide external heating or external cooling) to the optical projection system during operation. 25 [0011] According to some embodiments, there is a non-transitory computer-readable medium storing computer program instructions that, when executed by one or more processors, effectuates operations including any of the methods described above. [0012] According to some embodiments, there is a semiconductor processing apparatus including the optical projection system and the one or more thermal device, and wherein any of the methods 30 described above may be executed using the semiconductor processing apparatus. BRIEF DESCRIPTION OF THE DRAWINGS [0013] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments and, together with the description, explain these 35 embodiments. Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which: 4 [0014] Fig. 1 illustrates a block diagram of various subsystems of a lithographic projection apparatus, according to an embodiment of the present disclosure. [0015] Fig. 2 illustrates an exemplary flowchart for fully simulating lithography in a lithographic projection apparatus, according to an embodiment of the present disclosure. 5 [0016] Fig. 3 illustrates dynamic aberration correction based on semiconductor processing metrics per-substrate (e.g., per wafer or even per layer), according to an embodiment of the present disclosure. [0017] Fig. 4A illustrates an exemplary flowchart for determining process parameters associated with a thermal device, according to an embodiment of the present disclosure. [0018] Fig. 4B illustrates another exemplary flowchart for determining process parameters associated 10 with a thermal device, according to an embodiment of the present disclosure. [0019] Fig. 5 illustrates an example optical projection system including optical elements, according to an embodiment of the present disclosure. [0020] Figs. 6A and 6B illustrate an example heating state of an example optical element of an optical projection system, and an optical element deformation map, respectively, according to an 15 embodiment of the present disclosure. [0021] Fig. 7 illustrates an example optical element and adjustments capable of being made to a configuration of the optical element, according to an embodiment of the present disclosure. [0022] Fig. 8 illustrates an optical element and a set of thermal devices providing thermal energy to the optical element, according to an embodiment of the present disclosure. 20 [0023] Fig. 9 illustrates an example optical projection system including optical elements, thermal devices used to provide thermal energy to some or all of the optical elements, and control devices for controlling an orientation of some or all of the optical elements, according to an embodiment of the present disclosure. [0024] Figs. 10A and 10B illustrate example methods for performing offline and online thermal 25 correction for one or more optical elements of an optical projection system, according to an embodiment of the present disclosure. [0025] Figure 11 is a schematic diagram of a lithographic projection apparatus, according to an embodiment of the present disclosure. [0026] Figure 12 is a schematic diagram of another lithographic projection apparatus, according to an 30 embodiment of the present disclosure. [0027] Figure 13 is a detailed view of a lithographic projection apparatus, according to an embodiment of the present disclosure. [0028] Figure 14 is a detailed view of the source collector module of the lithographic projection apparatus, according to an embodiment of the present disclosure. 35 [0029] Figure 15 is a block diagram of an example computer system, according to an embodiment of the present disclosure. 5 DETAILED DESCRIPTION [0030] Being able to control or correct for wavefront drift induced by optical heating in semiconductor manufacturing processes is advantageous. For example, by correcting for wavefront drift in a lithography system, where the wavefront drift is induced by the heating of optical elements 5 of the lithography system (e.g., mirrors, lenses, etc.), defects in devices fabricated via one or more of the semiconductor manufacturing processes may be significantly reduced. [0031] In lithography systems, mirror heating, lens heating, and/or other dynamically changing factors to the production of patterned devices, such as semiconductor devices, can cause defects (e.g., edge placement errors, overlay errors, etc.). This demands fast and precise in-situ correction 10 capabilities to achieve stable imaging performance in production manufacturing environments. For example, mirror heating can cause wavefront drift, which is when a wavefront provided by an optical projection system of the lithography system differs from a target wavefront to be provided by the optical projection system. [0032] One prior attempt at this fast in-situ control included definition of a merit function based on 15 pupil level properties (e.g., RMS of a delta wave front with respect to a reference state) of a scanner, but was unaware of the imaging performance properties on a substrate (e.g., wafer) level. As a consequence, although aberrations on the pupil level were minimized, the imaging performance (on the substrate or wafer level) was not optimized. [0033] An alternative imaging performance based approach includes calculation of the Zernike 20 sensitivities of vast numbers of critical dimensions. Using this approach, lithography performance metrics are limited to critical dimensions. This approach is not flexible enough to cover other types of custom metrics including discrete metrics (e.g. defect counts, etc.). A different approach involves a method for matching the performance of different scanners by performing aberration (wave front) optimization using a source mask optimization engine. However, this approach was designed for a 25 cold lens setup without considering mirror heating and it performs an iterative optimization, which requires a full imaging simulation for every iteration. This is computationally heavy and unsuitable for dynamic in-situ scanner control. Still another different approach uses a calibrated aberration impact model configured to receive patterning system aberration data and determine new patterning process impact data for the received patterning system aberration data. However, this approach is no 30 longer sufficient due to the limited amount of rigid body mirror movements in the projection optics box (POB) of the driver lens model (DLM) to apply wavefront correction to mitigate the mirror heating impact for EUV scanners, which operate at high source power. [0034] Embodiments of the present application are described in detail with reference to the drawings, which are provided as illustrative examples of the disclosure so as to enable those skilled in the art to 35 practice the disclosure. Notably, the figures and examples below are not meant to limit the scope of the present disclosure to a single embodiment, but other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements 6 of the present disclosure can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present disclosure will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the disclosure. Embodiments described as being implemented in 5 software should not be limited thereto, but can include embodiments implemented in hardware, or combinations of software and hardware, and vice-versa, as will be apparent to those skilled in the art, unless otherwise specified herein. In the present specification, an embodiment showing a singular component should not be considered limiting; rather, the disclosure is intended to encompass other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated 10 otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present disclosure encompasses present and future known equivalents to the known components referred to herein by way of illustration. [0035] Although specific reference may be made in this text to the manufacture of ICs, it should be 15 explicitly understood that the description herein has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the term...