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1 METHOD OF WAFER GROUNDING UTILIZING WAFER EDGE BACKSIDE COATING EXCLUSION AREA FIELD 5 [1] The description herein relates to the field of semiconductor manufacturing, and more particularly to wafer grounding and biasing that may be useful for semiconductor wafer processing using a charged particle beam apparatus. BACKGROUND 10 [2] A charged particle beam apparatus is able to produce a 2-dimensional image of a wafer substrate by detecting secondary electrons, backscattered electrons, mirror electrons, or other kinds of electrons from the surface of the wafer substrate upon impingement by a charged particle beam generated by the charged particle beam apparatus. Various charged particle beam apparatuses are used on semiconductor wafers in the semiconductor industry for various purposes such as wafer 15 processing (e.g., e-beam direct write lithography system), process monitoring (e.g., critical dimension scanning electron microscope (CD-SEM)), wafer inspection (e.g., e-beam inspection system), defect analysis (e.g., defect review SEM, or DR-SEM and Focused Ion Beam system, or FIB), etc. When such apparatus performs its function, for better imaging, the electrical potential of the wafer substrate may be held at a predetermined value or be biased. This can be achieved by electrically, or more specifically, 20 resistively connecting the target wafer substrate to a programmable DC voltage source (e.g., a wafer bias supply). Electrical connection may be made when the wafer substrate interacts with the charged particle beam, during which excess charges are brought to the wafer substrate. This process can be referred to as wafer biasing. [3] For wafer biasing, electrical contact from the wafer bias supply to the wafer substrate is 25 conventionally made at the backside of the wafer substrate by using one or more electrical contacts that press against the backside surface of the wafer substrate. The front surface of the wafer is usually inappropriate to place the electrical contact because features are formed on the front surface. Sometimes a wafer has an electrically insulating film located on its backside surface (e.g., a backside film). The backside film can cause difficulty in establishing a reliable electrical connection between the electrical 30 contacts and a conductive surface of the wafer. SUMMARY [4] Embodiments of the present disclosure include systems and methods for wafer grounding using an exclusion area on a wafer backside film. In some embodiments, the exclusion area is a region 35 on the backside surface in which the backside film material is not present. Embodiments of the present disclosure provide a clean contact between an electrical contact (such as a grounding pin) and a conductive surface of a wafer. 2 [5] Embodiments of the present disclosure include a wafer having an exclusion area of a backside film for grounding the wafer. The exclusion area may be located, e.g., at a periphery of the wafer backside, at a central region, or at an intermediate region between the center and periphery. [6] Embodiments of the present disclosure include a wafer grounding system having a grounding 5 pin for contacting an exclusion area of a backside film. The grounding pin and exclusion area may be located, e.g., at a periphery of the wafer backside, at a central region, or at an intermediate region between the center and periphery. [7] Embodiments of the present disclosure include a charged particle beam inspection method for inspecting a wafer having an exclusion area on a backside film. The method may include inspecting the 10 wafer in two different inspection steps with the wafer supported at two different angular orientations in the wafer plane. One or more exclusion areas are configured so that the wafer may be grounded at an exclusion area during both inspection steps. [8] Embodiments of the present disclosure include systems and methods for manufacturing a wafer having a backside film exclusion area. Various exemplary systems and methods are disclosed for 15 masking or otherwise preventing film formation on a selected area during the process of forming a thick backside film in a processing chamber. [9] Further objects and advantages of the disclosed embodiments will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the embodiments. Some objects and advantages of the disclosed embodiments may be realized and 20 attained by the elements and combinations set forth in the claims. However, embodiments of the present disclosure are not necessarily required to achieve such exemplary objects or advantages, and some embodiments may not achieve any of the stated objects or advantages. [10] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, 25 as may be claimed. BRIEF DESCRIPTION OF THE DRAWINGS [11] Fig. 1 is a schematic diagram illustrating an example electron beam inspection (EBI) system, consistent with embodiments of the present disclosure. 30 [12] Fig. 2 is a schematic diagram illustrating an example electron beam tool, consistent with embodiments of the present disclosure that may be a part of the example electron beam inspection system of Fig. 1 . [13] Fig. 3 is an illustration of an example system of wafer grounding, consistent with embodiments of the present disclosure. 35 [14] Figs . 4A-4D illustrate operation stages of an example system for wafer grounding in a comparative embodiment. [15] Fig. 5 is an illustration of a potential issue caused by holes in a wafer backside-film. 3 [16] Figs. 6A-C are illustrations of an example subsystem for wafer grounding consistent with embodiments of the present disclosure. [17] Fig. 6D illustrates an example relationship between exclusion area radial positions, size and rotational positioning accuracy, consistent with embodiments of the present disclosure. 5 [18] Figs. 7A-B are illustrations of an example subsystem for wafer grounding consistent with embodiments of the present disclosure. [19] Figs. 8A-B are illustrations of an example subsystem for wafer grounding consistent with embodiments of the present disclosure. [20] Figs. 9A-B are illustrations of an example subsystem for wafer grounding consistent with 10 embodiments of the present disclosure. [21] Fig. 10 is an illustration of example wafers having backside film exclusion areas consistent with embodiments of the present disclosure. [22] Fig. 11A is an illustration of an example backside film formation chamber in a comparative embodiment of the present disclosure. 15 [23] Fig. 11B is an illustration of an example wafer backside film that may be formed in the chamber of Fig. 11A in a comparative embodiment of the present disclosure. [24] Fig. 12A is an illustration of an example backside film formation chamber consistent with embodiments of the present disclosure. [25] Fig. 12B is an illustration of an example wafer backside film that may be formed in the 20 chamber of Fig. 12A consistent with embodiments of the present disclosure. [26] Fig. 12C is an illustration of an example backside film formation chamber consistent with embodiments of the present disclosure [27] Fig. 13A is an illustration of an example backside film formation chamber in a comparative embodiment of the present disclosure. 25 [28] Fig. 13B is an illustration of an example wafer backside film that may be formed in the chamber of Fig. 13A in a comparative embodiment of the present disclosure. [29] Fig. 14A is an illustration of an example backside film formation chamber consistent with embodiments of the present disclosure. [30] Fig. 14B is an illustration of an example wafer backside film that may be formed in the 30 chamber of Fig. 14A consistent with embodiments of the present disclosure. [31] Fig. 15 is a flowchart illustrating an example method for forming a wafer backside film, consistent with embodiments of the present disclosure. [32] Fig. 16 is a flowchart illustrating an example method for grounding a wafer having a backside film, consistent with embodiments of the present disclosure 35 DETAILED DESCRIPTION 4 [33] Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of example 5 embodiments do not represent all implementations consistent with the disclosure. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the subject matter recited in the appended claims. Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing detection systems and detection methods in systems utilizing electron beams (“e-beams”). However, the disclosure is not so limited. Other types of charged-particle 10 beams (e.g., including protons, ions, muons, or any other particle carrying electric charges) may be similarly applied. Furthermore, systems and methods for detection may be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, or the like. [34] Electronic devices are constructed of circuits formed on a piece of semiconductor material called a substrate. The semiconductor material may include, for example, silicon, gallium arsenide, 15 indium phosphide, or silicon germanium, or the like. Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs. The size of these circuits has decreased dramatically so that many more of them can be fit on the substrate. For example, an IC chip in a smartphone can be as small as a thumbnail and yet may include over 2 billion transistors, the size of each transistor being less than 1/1000th the size of a human hair. 20 [35] Making these ICs with extremely small structures or components is a complex, time- consuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to result in defects in the finished IC, rendering it useless. Thus, one goal of the manufacturing process is to avoid such defects to maximize the number of functional ICs made in the process; that is, to improve the overall yield of the process. 25 [36] One component of improving yield is monitoring the chip-making process to ensure that it is producing a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection can be carried out using a scanning charged-particle microscope (“SCPM”). For example, an SCPM may be a scanning electron microscope (SEM). A SEM can be used to image these extremely small structures, in effect, 30 taking a “picture” of the structures of the wafer. The image can be used to determine if the structure was formed properly in the proper location. If the structure is defective, then the process can be adjusted, so the defect is less likely to recur. [37] The working principle of a SEM is similar to a camera. A camera takes a picture by receiving and recording intensity of light reflected or emitted from people or objects. A SEM takes a “picture” by 35 receiving and recording energies or quantities of electrons reflected or emitted from the structures of the wafer. Before taking such a “picture,” an electron beam may be projected onto the structures, and when the electrons are reflected or emitted (“exiting”) from the structures (e.g., from the wafer surface, 5 from the structures underneath the wafer surface, or both), a detector of the SEM may receive and record the energies or quantities of those electrons to generate an inspection image. To take such a “picture,” the electron beam may scan through the wafer (e.g., in a line-by-line or zig-zag manner), and the detector may receive exiting electrons coming from a region under electron-beam projection (referred 5 to as a “beam spot”). The detector may receive and record exiting electrons from each beam spot one at a time and join the information recorded for all the beam spots to generate the inspection image. Some SEMs use a single electron beam (referred to as a “single-beam SEM”) to take a single “picture” to generate the inspection image, while some SEMs use multiple electron beams (referred to as a “multi- beam SEM”) to take multiple “sub-pictures” of the wafer in parallel and stitch them together to generate 10 the inspection image. By using multiple electron beams, the SEM may provide more electron beams onto the structures for obtaining these multiple “sub-pictures,” resulting in more electrons exiting from the structures. Accordingly, the detector may receive more exiting electrons simultaneously and generate inspection images of the structures of the wafer with higher efficiency and faster speed. [38] Typically, the structures are made on a substrate (e.g., a silicon wafer) that is placed on a 15 platform, referred to as a stage, for imaging. When the electron beams hit the structures, they may charge the substrate and make the substrate no longer electrically neutral. The charged substrate may obtain a voltage and affect the exiting electrons, which may affect the imaging quality. Accordingly, to improve imaging, it may be advantageous to ground the substrate. [39] For grounding, the substrate may be electrically connected to an electric power sour...