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1 RETICLE FRONTSIDE POTENTIAL CONTROL WITH CLAMP BURL CONNECTION FIELD OF THE INVENTION [0001] The present invention relates to systems and methods for reducing particle formation on 5 reticles. BACKGROUND OF THE INVENTION [0002] During various types of lithography, particle formation can create significant defects and result in yield loss. Defectivity is often measured as added particles per reticle pass (PRP), which is 10 typically measured as the added particles on a reticle per 10000 wafers. [0003] For example, in EUV lithography, during EUV pulses, the EUV beam exposes the reticle. In effect there are two sources of electrons released in the reticle mini environment (RME): 1) from the photo-electric effect (expelled from reticle) and 2) electrons from photo-ionizations in the volume. Because electrons are released from the reticle, the reticle frontside gets a positive charge (not all 15 electrons return to reticle). The cumulative effect of all the electrons along with the EUV plasma result in negatively charged particles in the RME, which then get attracted to the positively charged reticle frontside causing an increase in PRP. [0004] There is a continuing need to reduce PRP to improve yield. 20 BRIEF DESCRIPTION OF THE DRAWINGS [0005] FIG. 1 schematically depicts a lithography apparatus, according to an embodiment. [0006] FIG. 2 schematically depicts an embodiment of a lithographic cell or cluster, according to an embodiment. [0007] FIG. 3 is a schematic diagram of a lithographic projection apparatus similar to FIG. 1, 25 according to an embodiment. [0008] FIG. 4 schematically depicts a more detailed view of the lithographic projection apparatus. [0009] FIG. 5 schematically depicts a reticle clamp. [0010] FIG. 6 schematically depicts a cross-sectional view of an exploded reticle clamp. [0011] FIG. 7 schematically depicts a clamping function of the reticle clamp. 30 [0012] FIG. 8 schematically depicts a charged particle effect and biasing of the reticle when an exposure beam is on. [0013] FIG. 9 schematically depicts the charged particle effect and biasing of the reticle when the exposure beam is on. [0014] FIG. 10 schematically depicts the charged particle effect and biasing of the reticle when the 35 exposure beam is off. [0015] FIG. 11 schematically depicts an embodiment of an electrostatic reticle clamp. [0016] FIG. 12 schematically depicts an embodiment to achieve reticle frontside potential. 2 [0017] FIGS. 13A-13B schematically depict an embodiment to enable burl potential control. [0018] FIGS. 14A-14B schematically depict an embodiment to enable burl potential control and true ground. [0019] FIG. 15 schematically depicts an embodiment of the burl configuration. 5 DETAILED DESCRIPTION [0020] In general, a mask or reticle may be a transparent block of material that is covered with a pattern defined by a different, opaque material. Various masks are fed into a lithographic apparatus and used to form layers of a semiconductor device. The pattern defined on a given mask or reticle 10 corresponds to features produced in one or more layers of the semiconductor device. Often, a plurality of masks or reticles are automatically fed into a lithographic apparatus during manufacturing and used to form corresponding layers of a semiconductor device. A clamp (e.g., an electrostatic reticle clamp) in the lithographic apparatus is used to secure a masks or reticles during processing. This clamp may become contaminated with particles of material transferred from reticles causing 15 performance degradation over time, and requiring periodic cleaning to restore performance. [0021] Cleaning these clamps can require stopping the lithographic apparatus and the manufacturing process. This cleaning can require several hours to complete, expose the environment inside the lithographic apparatus to ambient conditions, may introduce other contaminants into the system, and/or have other disadvantages. In addition, there is a flushing process where extremely 20 clean dry air (XCDA) is cycled through the chamber to remove the particles, but this too requires multiple hours and is not completely effective in cleaning these particles since particles still end up on the frontside of the reticle impacting PRP performance. [0022] In contrast to prior approaches, the present systems and methods provide a system where particles are repelled from the reticle frontside and hence do not adhere to the reticle frontside. In the 25 present systems and methods, a grounded pin in a electrostatic reticle clamp is repurposed to function as a reticle frontside potential connection. A strip of conductive coating (e.g., Cr, TiN) can be routed from an ear section of the clamp to a small portion of burls on the clamp. This connection can drive a slightly positive voltage, 5-10V, for example. The reticle can include a conductive coating electrically connecting the backside of the clamp to the frontside. When the backside of the reticle 30 contacts the electrically connected clamp burls, voltage can be supplied from the grounding pins, through the conductive coating on the clamp, to the conductive coating on the reticle. The frontside of the reticle then has a positive charge and can repel particles. [0023] Although specific reference may be made in this text to the manufacture of integrated circuits (ICs), it should be understood that the description herein has many other possible applications. 35 For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any 3 use of the terms “reticle”, “wafer” or “die” in this text should be considered as interchangeable with the more general terms “mask”, “substrate” and “target portion”, respectively. In addition, any use of the terms “reticle” or “mask” herein may be considered synonymous with the more general term “patterning device.” 5 [0024] As an introduction, prior to transferring a pattern from a reticle such as a mask to a substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures (“post-exposure procedures”), such as a post-exposure bake (PEB), development, a hard bake and measurement and/or other inspection of the transferred pattern. This array of procedures is used as a basis to make an 10 individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemical mechanical polishing, etc., all intended to finish an individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by 15 a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. [0025] Manufacturing devices, such as semiconductor devices, typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the devices. Such layers and features are typically manufactured and 20 processed using, e.g., deposition, lithography, etch, chemical mechanical polishing, ion implantation, and/or other processes. Multiple devices may be fabricated on a plurality of dies on a substrate and then separated into individual devices. This device manufacturing process may be considered a patterning process. A patterning process involves a patterning step, such as optical and/or nanoimprint lithography using a reticle in a lithographic apparatus, to transfer a pattern on the reticle 25 to a substrate and typically, but optionally, involves one or more related pattern processing steps, such as resist development by a development apparatus, baking of the substrate using a bake tool, etching using the pattern using an etch apparatus, etc. One or more metrology processes are typically involved in the patterning process. [0026] Lithography is a step in the manufacturing of device such as ICs, where patterns formed on 30 substrates define functional elements of the devices, such as microprocessors, memory chips, etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro- electromechanical systems (MEMS) and other devices. [0027] As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced while the number of functional elements, suc...